The present invention generally relates to memory devices, and more particularly, memory device testing.
In the area of memory failure analysis, memory devices may be susceptible to a phenomenon known as soft errors, where radioactive particles may cause memory cells to logically flip (i.e., change logic state). A soft error rate (SER) tester may, accordingly, be utilized to detect such soft errors in a laboratory-controlled radioactive environment in order to analyze the memories' soft error rate (SER).
In the area of SER failure analysis, testers have traditionally been designed to detect when a radioactive particle causes a single memory cell to logically flip. This single memory cell logic state change may be known as a single-bit upset (SBU). However, as the physical separation between adjacent memory cells continues to decrease with the scaling of modern devices, a new error is beginning to occur, whereby a radioactive particle may causes several local memory cells to logically flip. This multiple memory cell logic state change may be known as a multi-bit upset (MBU). The detection of MBU's may pose challenges for the present generation of SER testers since error detection occurs at low PC speeds while the tester cycles through the memory device under test (DUT) at relatively higher generator speeds.